The present invention is directed to integrated circuits and, more particularly, to a voltage clamping circuit.
Electrical overstress (EOS) failures of semiconductor devices are generally thermally-induced, electromigration-related and electric field-related. EOS reliability issues are encountered in circuit design especially for high voltage circuits or multiple power domain circuits. To avoid EOS, there are strict rules on the voltage difference applied to the terminals of circuit elements such as metal-oxide semiconductor field-effect transistors (MOSFETs). Voltages that do not respect these rules can lead to failures or reduced life time of the semiconductor devices.
The designer should keep the semiconductor devices safe under all operation conditions. However, process-voltage-temperature (PVT) variations and load variations are difficult to control or predict during the design stage. There is a need to clamp the voltages applied to a sensitive semiconductor device into the safe region in spite of unexpected PVT and load variation effects, that is to say limit physically the maximum voltage differences applied across sensitive terminals of the semiconductor device.
An on-chip voltage clamp for protecting semiconductor devices against EOS is sought having an accurate clamping voltage in spite of PVT and load variations, while enabling the clamping voltage to be programmed to suit different circuits, and without adding excessive cost to the design.